1. Field of the Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a polycide dual gate.
2. Description of the Related Art
When integration of elements in integrated circuit (IC) increases to achieve deep sub-micron processes, a dual gate having N-type gate and P-type gate is necessary. A tungsten silicide layer having low resistance is formed on a doped polysilicon layer, and then the tungsten silicide layer and the doped polysilicon layer are defined to form a polycide gate.
FIG. 1 is schematic three-dimensional view showing a conventional polycide dual gate. Referring to FIG. 1, a substrate 40 is provided, a gate oxide layer 42 is deposited on the surface of the substrate 40, and a polysilicon layer 44 is formed on the gate oxide layer 42. An N-type and P-type ion implantation step is performed on the polysilicon layer 44 to form a dual gate 48; the dual gate 48 comprises an N-type (or P-type) gate 44' and P-type (or N-type) gate 44". The tungsten silicide layer 46 is directly formed on the polysilicon layer 44 to increase conductivity of the dual late 48. The method causes the interdiffusion 50 of N-type and P-type ions in the dual gate 48 through the tungsten silicide layer 46 while a thermal process is performed, and the interdiffusion 50 phenomenon will induce devices failure.
FIGS. 2A through 2C are schematic. cross-sectional views showing the progression of another conventional manufacturing steps for a polycide dual gate. Referring to FIG. 2A, a substrate 10 that has an isolation structure 11 is provided; the isolation structure 11 is filled with insulation material. A gate oxide layer 12 is deposited on the surface of the substrate 10, a polysilicon layer 14 is deposited on the gate oxide layer 12, and an oxide layer 16 is formed on the polysilicon layer 14 by chemical oxidation (or chemical vapor deposition or thermal oxidation). A amorphous silicon layer 18 (.alpha.-Si layer ) is formed on the surface of the oxide layer 16, and an N-type and P-type ions implantation step is performed. An annealing step is performed to restore the surface crystal structure of the .alpha.-Si layer 18, and then a tungsten silicide layer 20 is formed over the .alpha.-Si layer 18. Since the N-type and the P-type ions in the dual gate diffuse through the tungsten silicide layer 20 while a thermal process is performed, in this invention, the oxide layer 16 is provided as a impurity diffusion barrier layer in order to prevent the interdiffusion. Because the tungsten silicide layer 20 does not have good adhesion with the oxide layer 16, hence the .alpha.-Si layer 18 having low resistance is formed between the tungsten silicide layer 20 and the oxide layer 16 to improve the adhesion and the conductivity, then a stack structure comprising the tungsten silicide layer/.alpha.-Si layer/oxide layer/polysilicon layer/gate oxide layer is made. However, the stack structure results in increased RC time delay of the polysilicon layer 14 and easily changes the original MOS structure into an E.sup.2 PROM structure. This change will affect device performance.
Referring to FIG. 2B, the tungsten silicide layer 20, the .alpha.-Si layer 18, the oxide layer 16, the polysilicon layer 14 and the gate oxide layer 12 are defined to become a tungsten silicide layer 20a, an .alpha.-Si layer 18a, an oxide layer 16a, a polysilicon layer 14a and a gate oxide layer 12a by dry etching to form a gate region. The gate region is used as a mask, and a lightly doped source/drain region 22 is formed beside the gate in the substrate 10 by an ion implantation step. A silicon dioxide layer 24 is formed conformal to the substrate 10.
As shown in FIG. 2C, a spacer 24a is formed on the sidewall of the gate when the silicon dioxide layer 24 is etched back by dry etching. The spacer 24a and the gate are used as a mask, and a heavily doped source/drain region 26 is formed beside the spacer 24a in the substrate 10 by an ion implantation step. An annealing step is performed to restore the surface crystal structure of the heavily doped source/drain region 26 by rapid thermal processing (RTP).
Semiconductor miniaturization results in increasing the contact resistance of the interface between different layers. Therefore the dopant concentration of contact surface must be sufficient high to attain sufficient low contact resistance. In the conventional method for forming a polycide dual gate, the .alpha.-Si layer has a low dopant concentration, hence the RC time delay of polysilicon gate is still high. The oxide layer prevents interdiffusion of dopants but results in changing the original MOS structure into an E.sup.2 PROM or EPROM structure, which change will affect device performance. The .alpha.-Si layer is formed between the tungsten suicide and the oxide layer to enhance adhesion between both of them, but the structure becomes complicated.